Notes on FPGA's , 1

I put here some notes to supplement the book "Introduction to Programmable Logic, Programmable Logic Design Quick Start Handbook" from Xilinx, that I received along with their Spartan-3E starter kit.

Complex Programmable Logic Device is a PLD with complexity between that of PAL`s and FPGA`s. wikipedia
CPLD -> is made using interconnected SPLD`s (Simple PLD`s) which are small programming module like PLA or PAL. CPLD consists of gates, numbering from some thousands upto one lakh(100 thousand).

FPGA -> contains CLB's(Configurable Logic Blocks) and routing channels. CLB has a 4-input LUT and a D- FlipFlop. FPGA contain more than a million gates(Xilinx Virtex-II--exceeds 10 million mark) to implement logic functions.


PLA vs. PAL -> Programmable Logic Array is bigger, has higher fuse count, more flexible but slower and has more complex software than Programmable Array Logic. PAL has only one programmable plane- OR is fixed, AND is programmable.

Why programmable logic:
1) It is economical to produce and IC in large volumes.
2) Many designs require only small volumes of IC's.

Advantages of programmable logic:
1. Can be made in large volumes
2. Can be programmed to implement large no of different low volume designs
3. Field-programmable, i.e.-programmed outside manufacturing environment
4. Erasable, reprogrammable, can be updated or corrected, re-usable.
5. Used for prototyping of designs to be implemented into regular IC's

Discrete logic -> Separate device for each logic function
PLD provides 50 times more gates in a packagethan discrete logic devices.

Form Factor (from Webopedia) -> The physical size and shape of a device. It is often used to describe the size of circuit boards.

Pin pitch must be spacing between the pins its 0.5 mm for Xilinx CoolRunner CPLD.

Level of integration is no of system gates per area.

Cost of ownership is the cost to maintain, fix or warranty a product.

FIT is failure in time of device. Means the no of device failures statistically expected for a certain no of device hours, expressed as failures per 1 billion device hours with device temperature specified. Lower heat dissipiation and lower power operation leads to decreased FIT in coolrunner CPLD.