Notes on FPGA's, 2

ABEL (Advanced Boolean Equation Language) allows you to enter behavior-like descriptions of a logic circuit. ABEL is an industry-standard hardware description language (HDL) that was developed by Data I/O Corporation for programmable logic devices (PLD). There are other hardware description languages such as VHDL and Verilog. ABEL is a simpler language than VHDL which is capable of describing systems of larger complexity.

ABEL can be used to describe the behavior of a system in a variety of forms, including logic equations, truth tables, and state diagrams using C-like statements. The ABEL compiler allows designs to be simulated and implemented into PLDs such as PALs, CPLDs and FPGAs.
Reference: ABEL Primer

Netlist -> is the text-equivalent of a circuit.

A schematic capture program generates a netlist.
Names of components may be ...G1, G2, G3(G for gate)
Names of nets can be...N1, N2 etc..
Input package pins can be A,B,C,D etc.
Output pins cab be Q,R,S


Typical schematic page contains 200 gates.
10,000 gates need 50 pages.


Schematic capture with gates is vendor-specific.

Better way: HDL(hardware description language), HLD(high level design), behavioral description----These describe ckt(circuit) in text file rather than low level graphical description.Function/behavior of ckt is described.

2 flavors of HDL
Verilog
VHDL


HDL is
-> easy to use
-> vendor independent
-> reusable




After behavioral description covert design into gates---process called synthesis.

Synthesis is done manually in schematic capture.


Synthesis tools support large range of FPGA and CPLD device vendors.


Mapping can be done additionally. This is for optimization of design...
various criteria can be complete design for
->least no of gates,
-> optimize a part of ckt for fastest speed
-> minimize power
-> FPGA-friendly register-rich config. for state machines.



Easily explore different vendors, device families and optimization constraints to get many solutions.



Intellectual Property IP cores
complex pre-tested system level functions used for logic design. like PCI bus interface, DSP filter, PCIMCIA interface. are extensively tested, are rarely free, need minimum to 0 time to verify.IP cores are available in HDL format..so easy to modify and use in different devices of different vendors.

After design spec is finished, we need to know if ckt is doing what it is supposed to do. This is the task of design verification.
Design verification: using simulator, software program for confirming functionality and timing of ckt.

Simulator takes in the netlist(out of schematic capture or synthesis) and specific input pattern or test vectors..that are to be checked. Simulator takes this info and determines the o/p of the ckt.

Schematic Capture of an FPGA Design

Below is the link to my very first attempt to draw the simplest mind map on www.mind42.com.

schematic capture: design flow

Notes on FPGA's , 1

I put here some notes to supplement the book "Introduction to Programmable Logic, Programmable Logic Design Quick Start Handbook" from Xilinx, that I received along with their Spartan-3E starter kit.

Complex Programmable Logic Device is a PLD with complexity between that of PAL`s and FPGA`s. wikipedia
CPLD -> is made using interconnected SPLD`s (Simple PLD`s) which are small programming module like PLA or PAL. CPLD consists of gates, numbering from some thousands upto one lakh(100 thousand).

FPGA -> contains CLB's(Configurable Logic Blocks) and routing channels. CLB has a 4-input LUT and a D- FlipFlop. FPGA contain more than a million gates(Xilinx Virtex-II--exceeds 10 million mark) to implement logic functions.


PLA vs. PAL -> Programmable Logic Array is bigger, has higher fuse count, more flexible but slower and has more complex software than Programmable Array Logic. PAL has only one programmable plane- OR is fixed, AND is programmable.

Why programmable logic:
1) It is economical to produce and IC in large volumes.
2) Many designs require only small volumes of IC's.

Advantages of programmable logic:
1. Can be made in large volumes
2. Can be programmed to implement large no of different low volume designs
3. Field-programmable, i.e.-programmed outside manufacturing environment
4. Erasable, reprogrammable, can be updated or corrected, re-usable.
5. Used for prototyping of designs to be implemented into regular IC's

Discrete logic -> Separate device for each logic function
PLD provides 50 times more gates in a packagethan discrete logic devices.

Form Factor (from Webopedia) -> The physical size and shape of a device. It is often used to describe the size of circuit boards.

Pin pitch must be spacing between the pins its 0.5 mm for Xilinx CoolRunner CPLD.

Level of integration is no of system gates per area.

Cost of ownership is the cost to maintain, fix or warranty a product.

FIT is failure in time of device. Means the no of device failures statistically expected for a certain no of device hours, expressed as failures per 1 billion device hours with device temperature specified. Lower heat dissipiation and lower power operation leads to decreased FIT in coolrunner CPLD.